Modeling, and Experimental Measurements, of the SER Critical Charge (Qcrit) in Scaled, SOI, CMOS Devices
نویسندگان
چکیده
Trends in modeling and measurements of the Soft Error Rate (SER) critical charge (Qcrit) for recent generation CMOS SOI devices are reviewed. Modeling and measurements as a function of voltage on 65, 45, 32 and 22 nm planar, SOI devices will be presented. The modeling techniques used will be reviewed and, where possible, compared to experimental measurements. Finally modeling of new device structures (e.g., multifingered FinFET devices) will also be discussed.
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